# Wire Lang

> Wire Lang is a text-first language for electronic schematics. You describe a circuit as components, terminals, and nets in a small declarative `.wire` file, and Wire Lang renders it as a clean, deterministic SVG diagram. The same source always produces the same diagram.

Code is text, so AI can read it, write it, and refactor it. Diagrams followed with text formats like Mermaid, but electronic schematics stayed locked inside GUI editors that AI cannot read. Wire Lang is the missing layer between AI and the circuit board.

Wire Lang models a real electrical circuit — components with typed terminals joined by nets — rather than flowchart boxes and arrows. It is a documentation-oriented schematic renderer: it is NOT a simulator, a PCB or breadboard layout tool, or a bill-of-materials generator.

Key facts:
- Install: `npm install wire-lang` (open source, MIT, ESM-only, Node.js 20+).
- Source files use the `.wire` extension, are UTF-8, and start with the `schematic` keyword.
- Render from the CLI: `npx wire render file.wire --out file.svg`, or from JS/TS: `import { renderSvg } from "wire-lang"`.
- Two layout modes: the default `flow` layout, and `render layout=bus-rail` for block diagrams between a top supply rail and a bottom ground rail with color-coded nets and bundled bus trunks.
- Built for AI authoring: structured diagnostics with source locations and suggested fixes, JSON CLI output, and a bundled Agent Skill.

Minimal complete example:

```wire
schematic
  title "LED current limiting circuit"

  component BT1 Battery voltage=5V
  component R1 Resistor value=220ohm
  component D1 LED color=red

  net VCC: BT1.+, R1.1
  connect R1.2, D1.A
  net GND: D1.C, BT1.-

  annotation "Current limiting resistor" near R1
```

## Docs

- [Documentation overview](https://www.wirelang.net/docs/): What Wire Lang is and where to start.
- [Getting started](https://www.wirelang.net/docs/getting-started/): Install, write your first `.wire` file, and render it from the CLI or JavaScript.
- [Syntax reference](https://www.wirelang.net/docs/syntax/): Every statement — components, IC pins, local definitions, nets, connect, no-connect, power nets, render hints and layout modes, annotations, properties — and the full standard component library.
- [CLI usage](https://www.wirelang.net/docs/cli/): The `wire check`, `wire render`, and `wire watch` commands, JSON diagnostics, and exit codes.
- [Examples](https://www.wirelang.net/docs/examples/): Copy-pasteable `.wire` circuits with their rendered SVG output.
- [Wire Lang vs Mermaid](https://www.wirelang.net/docs/comparison/): How a text-first schematic language differs from a text-first diagram tool.
- [FAQ](https://www.wirelang.net/docs/faq/): What Wire Lang is, what it is not, and how it fits an AI authoring workflow.

## Standard component library

`Resistor`, `Capacitor`, `PolarizedCapacitor`, `Inductor`, `Diode`, `LED`, `NPNTransistor`, `PNPTransistor`, `Battery`, `GroundReference`, `SPSTSwitch`, `PushButton`, `Header`, `FerriteBead`, `TVSDiode`, `Speaker`, `Antenna`, `TestPoint`, `PTC`, `PowerFlag`, `IC`. `IC` is a generic chip whose numbered, named pins come from `pins=[1:VCC@left, 2:GND@left, 3:OUT@right]`. Other parts are declared locally with a `define component ... end` block.

## Canonical links

- Website: https://www.wirelang.net/
- Full docs as a single file: https://www.wirelang.net/llms-full.txt
- GitHub repository: https://github.com/eduardozf/wire-lang
- npm package: https://www.npmjs.com/package/wire-lang
- Agent Skill: `npx skills add eduardozf/wire-lang --skill wire-lang`

## Optional

- [Repository README](https://github.com/eduardozf/wire-lang#readme): Project overview, API summary, and example gallery.
- [MVP specification](https://github.com/eduardozf/wire-lang/blob/main/docs/MVP.md): The detailed language and scope specification.
- [Domain vocabulary](https://github.com/eduardozf/wire-lang/blob/main/docs/CONTEXT.md): Definitions of components, nets, terminals, and other domain terms.