Frequently asked questions

Short answers to the most common questions about Wire Lang — what it is, what it deliberately is not, the built-in components, and how it fits an AI-assisted authoring workflow.

What is Wire Lang?

Wire Lang is a text-first language for electronic schematics. You describe a circuit as components, terminals, and nets in a small declarative .wire file, and Wire Lang renders it as a clean, deterministic SVG diagram. It is a documentation-oriented schematic renderer with strong authoring feedback for humans, editors, and AI agents.

How is it different from Mermaid?

Both turn text into diagrams, but Mermaid draws generic flowchart boxes and arrows whose meaning is up to the author, while Wire Lang models a real electrical circuit: components with typed terminals joined by nets, validated against a component library, and rendered as an electronic schematic. Wire Lang is not a Mermaid plugin and does not aim for syntax compatibility. See the full Wire Lang vs Mermaid comparison.

Does it simulate circuits?

No. Wire Lang is a schematic documentation renderer. It does not perform electrical simulation, PCB layout, routing, breadboard layout, or bill-of-materials generation. Those are explicit non-goals. Simulation and BOM support are possible future plugins, not part of the current scope.

Can it lay out a PCB or breadboard?

No. A Wire Lang document is a logical schematic — it shows components and their electrical connections, not physical placement, board routing, or breadboard rows.

What components are built in?

The standard library includes Resistor, Capacitor, PolarizedCapacitor, Inductor, Diode, LED, NPNTransistor, PNPTransistor, Battery, GroundReference, SPSTSwitch, PushButton, Header, FerriteBead, TVSDiode, Speaker, Antenna, TestPoint, PTC, PowerFlag, and IC — a generic chip whose numbered, named pins come from a pins=[...] list. See the component library for terminals and properties.

What if I need a part that isn't built in?

For chips, use the built-in IC type with named pins, e.g. component U1 IC pins=[1:VCC@left, 2:GND@left, 3:OUT@right]. For anything else, define it locally with a define component ... end block, listing its terminals and choosing a symbol (usually symbol module for a generic block). MOSFETs, op-amps, and complex boards such as Arduino are modeled this way today.

Does it support different layouts?

Yes. The default flow layout draws components in a row with per-net rails. Adding render layout=bus-rail redraws the schematic as a block diagram between a top supply rail and a bottom ground rail, color-coding nets by family and bundling grouped signals into bus trunks. Power rails and buses are inferred from net names and connectivity — no extra syntax needed. See the layout modes section of the syntax reference.

How does it work with AI?

Because schematics are plain text, AI assistants can generate, read, and refactor them. The parser returns a partial AST even for invalid input; every diagnostic carries a source location and a suggested fix; and the CLI emits JSON (wire check file.wire --json) so agents can self-correct. A bundled Agent Skill teaches assistants the syntax and component library.

What file format does it use?

Source files use the .wire extension and are UTF-8. Each file contains exactly one document that begins with the schematic keyword. The renderer outputs standalone SVG that includes the styles it needs, accessible title/description text, and stable metadata.

Is there a preview server?

No. You preview a schematic by opening the generated SVG file directly. Use wire watch to re-render automatically as you edit.

Is it free and open source?

Yes. Wire Lang is MIT-licensed and published on npm as wire-lang. The source is on GitHub.

Are the symbols IEC compliant?

Standard symbols follow an IEC-style visual profile where practical, using original open-source artwork, but Wire Lang does not claim formal IEC 60617, IEEE 315, or other standards compliance.